(Invited) Advanced Compute Scaling: A New Era of Exciting, Sustainability-Aware Innovations with Nanosheet-Based Devices, Increased Interdisciplinary Synergies, and (R)Evolution Towards Higher Versatility

The need for increased computing keeps growing at an ultra-fast speed, required to support an ever larger and wider range of applications [1]. Meanwhile, recent advances in 3D and photonic technologies are allowing new connectivity possibilities besides the typical on-chip interconnects at system-on-chip (SoC) level. This is enabling a system (r)evolution towards smart disintegration, moving away from a one-meets-all-requirements general-purpose CMOS platform, and allowing higher flexibility by separately designing and fabricating the blocks that are assembled in the final system [2]. Boosted by the novel scaling options enabled by this new approach, logic standard cell shrinkage remains at the core of the compute roadmap. Its momentum is expected to carry on by introducing new device architectures, materials, and scaling boosters such as backside (BS) power delivery (PD) [3-9]. Guided by design-technology-co-optimization (DTCO)-driven design improvements, in close interaction with the adoption of system-technology-co-optimization (STCO), the roadmap also increasingly requires EUV/high-NA EUV lithography for cost-effective, lower energy consumption, continued dimensional scaling. At transistor level, finFETs are being replaced by nanosheet (NS) FETs consisting of several vertically stacked NS per device [10,11]. Beyond that, 3D stacked CMOS, also called CFET [9,12,13], where different polarity NSFETs are folded on top of each other, appears as the ultimate scaling limit of the NS-based transistor’s family. Moreover, changes in how devices are connected are also being introduced. Moving PD to the wafer’s BS, though being a considerable disruptive technological change, is a game changer for on-chip power distribution, enabling smaller IR-drop values. This concept can be implemented in various ways, and has the potential to expand towards other functions, namely by addition of specific devices after BS processing, paving the way towards a truly functional BS [3,9,14]. Two examples of benefits brought by increased BS use are: 1) considerably more compact ESD diodes, with improved latch-up immunity, and BS contacts [9,15]; 2) lower clock latency values by moving the clock’s signal to the BS [9,16]. Furthermore, as transistors are now sandwiched and accessed from levels above and below them, this also enables interesting new opportunities for device engineering. Focusing on the highly scalable BS PD scheme wherein the transistor’s source (S) (for bottom FET in case of CFET) is directly contacted from the BS (BSC-S) (Fig.1) [7,9,17,18], while the other terminals remain connected from the wafer’s frontside, several options to optimize the BSC-S’s contact resistance can be considered. These include ways to enlarge its contact surface area and the possible addition of an extra low-temperature, low-resistivity epitaxial layer [9,19,20] prior to metallization. Fig.2 also highlights the need to account for the impact on thermal performance when selecting (BSC-S)-based device configurations and materials [7,9]. Additionally, the intrinsically asymmetric S/drain (D) access with BSC-S can also be explored to enable a simpler path to build devices with differently doped S/D [9]. This can be especially interesting for high-mobility, low-bandgap FETs to mitigate I OFF concerns while still taking advantage of their high-drivability potential. CFET using, e.g., bonding technology for the bottom/top channels and their vertical isolation’s definition can also be particularly suitable for implementing distinct channel materials (like Ge-rich for bottom PMOS) as they are in separate planes. Overall, compute systems, guided by DTCO/STCO with the embrace of the use of both wafer sides, 3D stacking and sequential technologies, can potentially be assembled in ways enabling much more versatile, hybridized platforms. This can allow not only new paths for continued compute/logic scaling, but also ease the introduction of new/alternative device architectures (and materials) as they do not need to meet all the requirements of a general-purpose platform. References [1] Y.-J. Mii et al. , VLSI 2022, 276; [2] M. G. Bardon et al. , Imec ITF World 2023; [3] J. Ryckaert et al. , EDTM 2019, 50; [4] A. Veloso et al. , VLSI 2021, TFS2-6; [5] R. Chen et al. , IEDM 2021, 498; [6] A. Veloso et al. , VLSI 2022, 284; [7] A. Veloso et al. , IEDM 2022, 563; [8] M. Shamanna et al. , VLSI 2023, T1-1; [9] A. Veloso et al. , IEDM 2023, T19-2; [10] N. Loubet et al. , VLSI 2017, 230; [11] J. Jeong et al. , VLSI 2023, T1-2; [12] J. Ryckaert et al. , IEDM 2019, 685; [13] M. Radosavljević et al. , IEDM 2021, 721; [14] J. Ryckaert, Imec ITF Japan 2022; [15] K. Serbulova et al. , VLSI 2022, 431; [16] S. K. Lim, VLSI 2023, WS3-4; [17] S. C. Song et al. , IEDM 2021, 494; [18] M. Kobrinsky et al. , VLSI 2023, TFS2-1; [19] C. Porret et al. , IEDM 2022, 807; [20] N. Breil et al. , VLSI 2023, T1-5. Figure 1