Study of SRAM Standby Leakage Reduction Techniques for Deep-submicron CMOS Technology

With scaling down of the technology, share of leakage is increasing in total power consumption of Static Random Access Memories (SRAMs).This paper presents the detailed study of conventional and proposed 6T SRAM standby leakage reduction techniques for advanced technology node.A 6T SRAM bitcell, in 45 nm technology with size 0.38 μm 2 , has been designed.This study shows that the performance of these leakage reduction techniques depends on the composition of cell standby leakage in terms of its components, and the composition of cell standby leakage itself depends on technology as well as temperature.Finally, efficient combination of SRAM standby leakage reduction techniques for advanced technology, have been proposed here.