Parallel channel routing

A parallel algorithm is proposed for the problem of channel and switchbox routing in the design of VLSI chips. The algorithm is suitable for implementation on a shared-memory multiprocessor environment. The approach does not impose restrictions on the channel type (such as fixed or variable channel widths) and the number of available layers. The algorithm contains three major phases: (1) dividing the channel into several regions by selecting some columns, (2) assigning tracks to nets of the selected columns, and (3) assigning tracks to nets of the columns in each region.>