A Novel Vertically Stacked Circular Nanosheet FET for High-Performance Applications

Nanosheet MOSFETs with circular layout geometry, i.e. Circular Nanosheet MOSFETs (C-NSFETs) are explored using fully calibrated TCAD for High performance (HP) applications at 10 nm gate length. The DC parameters such as drive current (I ON ), leakage current (I OFF ), I ON/OFF current ratio, Subthreshold slope (SS), and Drain-induced-barrier lowering (DIBL) are extracted. Further, we analyzed the behavior of C-NSFETs by vertically stacking the number of sheets (2-sheet, 3-sheet, and 4-sheet) and named stacked Circular Nanosheet MOSFETs (SC-NSFETs) and also compared the variations of their DC FOMs (figures of merit), is observed that the device drive current level is further improving by stacking of multiple Nanosheets within the same foot-print. The drive current of the device with the stacking of 4 sheets has an improvement of ∼4 times when compared to single sheet C-NSFET.